The present invention relates to a method and/or architecture for data communications generally and, more particularly, to a method and/or architecture for auto-locking the frequency of an oscillator to a multiple of the rate of an incoming data stream.
Conventional communication circuits require a precision timing component to supply a reference frequency to an external device. The chip either uses such a reference frequency as is, or further tunes the frequency to match the data rate of incoming data. Conventional Phase Lock Loop (PLL) and/or Delay Lock Loop (DLL) circuits may be used to lock to such data rates, sometimes requiring long data xe2x80x9ctrainingxe2x80x9d sequences. Conventional approaches that use a local fixed reference frequency typically do some phase shifting or phase selection to sample incoming data since the clock rate between the internal clock and the external clock typically differ.
Precision timing elements used in such circuits are crystals, resonators etc. Interfacing to the timing element requires one or two pins of the chip, which adds to the overall cost of the chip. Precision timing elements also require additional inventory and board space. Internally based timers (e.g., PLLs) typically require long training sequence to tune a PLL/DLL, which may not be available in modern applications, such as Universal Serial Bus (USB) applications.
The present invention concerns a method for tuning the frequency of oscillation of a clock signal, comprising the steps of (A) analyzing the rate of an incoming data stream to generate one or more control signals and (B) adjusting said frequency of oscillation in response to said one or more control signals.
The objects, features and advantages of the present invention include providing a method and/or architecture for auto-locking the frequency of an oscillator with a data rate of an incoming data stream that may (i) be used in a data communication device, (ii) precisely lock to an incoming data rate without an external precision timing element, (iii) analyze incoming data traffic to provide precision timing, (iv) provide 1% (or greater) accuracy without an external timing element, and/or (v) provide a precise oscillator without requiring pins to interface to the chip.